The present disclosure relates generally to cache coherence and, more particularly, to techniques for effectively maintaining cache coherence between devices by tracking whether groups of one or more cache lines are possibly in use.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Electronic devices with multiple processors or other memory-sharing devices frequently employ cache coherence techniques to maintain the integrity of shared memory. Common cache coherence techniques may involve bus snooping, in which one processor may communicate snoop requests to another before accessing the desired memory. Such cache coherence techniques may produce acceptable results when processors operate on relatively moderate memory bandwidths. When one or more of the processors is a memory-sharing device that employs a particularly high memory bandwidth (e.g., a graphics processing unit, or GPU), however, excessive snoop traffic may result. For this reason, high-bandwidth devices such as GPUs are typically made non-coherent with other memory-sharing devices in the electronic device. Unfortunately, non-coherent devices may require specially written software to manage their non-coherent memory. As such, the use of high-performance, high-bandwidth processors for general computing tasks may be limited. For example, general processing on GPUs may require specialized programs written with explicit memory buffer management, which may be unappealingly taxing to software developers.